The doctoral dissertations of the former Helsinki University of Technology (TKK) and Aalto University Schools of Technology (CHEM, ELEC, ENG, SCI) published in electronic format are available in the electronic publications archive of Aalto University - Aaltodoc.
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Mixed-Mode Cellular Array Processor Realization for Analyzing Brain Electrical Activity in Epilepsy
Mika Laiho
Dissertation for the degree of Doctor of Science in Technology to be presented with due permission of the Department of Electrical and Communications Engineering for public examination and debate in Auditorium S4 at Helsinki University of Technology (Espoo, Finland) on the 28th of June, 2003, at 12 o'clock noon.
Dissertation in PDF format (ISBN 951-22-6598-2) [2776 KB]
Dissertation is also available in print (ISBN 951-22-6597-4)
Abstract
This thesis deals with the realization of hardware that is capable of computing algorithms that can be described using the theory of polynomial cellular neural/nonlinear networks (CNNs). The goal is to meet the requirements of an algorithm for predicting the onset of an epileptic seizure. The analysis associated with this application requires extensive computation of data that consists of segments of brain electrical activity. Different types of computer architectures are overviewed. Since the algorithm requires operations in which data is manipulated locally, special emphasis is put on assessing different parallel architectures. An array computer is potentially able to perform local computational tasks effectively and rapidly.
Based on the requirements of the algorithm, a mixed-mode CNN is proposed. A mixed-mode CNN combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks, whereas the integrator is digital. A/D and D/A converters are used to interface between the analog blocks and the integrator. Based on the mixed-mode CNN architecture a cellular array processor is realized. In the realized array processor the processing units are coupled with programmable polynomial (linear, quadratic and cubic) first neighborhood feedback terms. A 10 mm2, 1.027 million transistor cellular array processor, with 2×72 processing units and 36 layers of memory in each is manufactured using a 0.25 μm digital CMOS process. The array processor can perform gray-scale Heun's integration of spatial convolutions with linear, quadratic and cubic activation functions for 72×72 data while keeping all I/O operations during processing local. One complete Heun's iteration round takes 166.4 μs, while the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown. Descriptions regarding improvements in the design are also explained. The results of this thesis can be used to assess the suitability of the mixed-mode approach for implementing an implantable system for predicting epileptic seizures. The results can also be used to assess the suitability of the approach for implementing other applications.
Keywords: mixed-mode integrated circuits, analog arithmetic circuits, (polynomial) cellular neural/nonlinear networks, CMOS, discrete-time systems, cellular array processors
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© 2003 Helsinki University of Technology
Last update 2011-05-26